This description relates to computing in parallel processing environments.
FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) are two exemplary approaches for implementing customized logic circuits. Costs associated with ASICs include verification, physical design, timing closure, and non-recurring costs. Unlike an ASIC, an FPGA is reprogrammable in that it can be reconfigured for each application and changed even after the design has been shipped to customers, much like software can be updated. However, FPGAs are typically more expensive than an ASIC. FPGAs typically consume more power and have lower performance compared to an ASIC.
Multicore systems (e.g., tiled processors) use parallel processing to achieve some features of both ASICs and FPGAs. For example, some multicore systems are power efficient like an ASIC because they use custom logic for some functions, and reconfigurable like FPGAs because they are programmable in software. Other multicore systems are not tile based.
Multicore systems include cache memory and cache controller units. Cache can be multi-level, typically two or three levels and caches can be distributed and can be associated with cores of a multi core system. When caches are multi-level and/or distributed, generally it is necessary to have a coherency scheme. Several coherency schemes are known, including the so called “MESI protocol” an invalidate-based cache coherence protocol commonly used to with write-back caches. In MESI protocol there are four states—Modified, Exclusive, Shared, and Invalid.
Another cache coherency protocol is a variation of the MESI protocol, which includes an additional state, “an Owned state” and is commonly referred to as the MOESI protocol. The advantage of including an Owned state is that, while an owned line can be shared among many caches, the cache that owns the owned line has the exclusive right to modify the line, i.e., make the owned line a “dirty line” (a line that is modified within a cache, but not memory). The cache with the owned state for the dirty line has the responsibility to provide the latest value to other caches more broadly “new reader devices”, and to write the dirty line back to memory upon eviction from the owned cache “write-back” to memory. In this scheme all caches that have read the dirty line will have the same value, which is a different value from the value in memory (until the line is evicted from the cache and written back to memory).
Another variation of the MESI protocol is to add a Forward state (MESIF). The advantage of a Forward state is that one cache is designated as the one that must provide a cache line to new reader devices. That removes bandwidth from memory and is also potentially faster than having to read the cache line from memory. The cache with the forward state “set” notifies a cache directory when the cache evicts the line because that cache is no longer able to provide the cache line. However, the evicted line does not need to be written back to memory (as in the Owned state) because it has not been modified.